Integrated circuits (ICs) are typically fabricated with rows of input/output (I/O) pads positioned between the edge of the die and the active circuit area. The layout of a typical input/output (I/O) pad has the active area of the silicon die that performs the required I/O functions connected by a conductive path to an external wire bond pad. The external wire bond pad is used to connect the active circuitry of the device to the package pins, by bonding a metal wire between the external wire bond pad and a package bond finger. The I/O pad enables the core functions of the chip to connect with external signals, and the device power supply and ground voltages. The active circuitry of the device is normally not positioned within the die area under the wire bond pad. This is because of the likelihood of damage to the integrated circuit (IC) material under the wire bond pad when the wire connecting the wire bond pad to the package bond finger is compression bonded to the die. Because the cost of an IC device is directly related to the die area of an IC, significant attention has been paid to reducing the amount of die area occupied by wire bond pads.
Efforts are under way to develop fabrication techniques referred to as circuit under pad (CUP) approaches, in which the wire bond pads are fabricated within the active area of the IC device die. In particular, one method employs redundant active circuitry next to selected wire bond pads. The purpose of the redundant circuitry is to help determine whether structural damage to the IC due to the wire bonding operation has occurred. This technique, however, is restricted to use on IC devices that are limited by the amount of circuitry in the active area, and not by the number of I/O wire bond pads needed.
This methodology works only on a non-I/O limited design, because of the need to make room for the redundant circuits that are placed next to the wire bond pad. The size of the chip remains the same whether or not the circuit under pad is used. Bonding on top of the redundant circuit may be performed to help prove that there is no structural damage. This approach may be a single-step, circuit under pad methodology, because it requires only a single all-layer mask spin. Such an implementation is inefficient, because this approach assumes that the chip is not I/O wire bond pad limited.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.